Panel array
Step-and-repeat panels with tooling strips both sides. Panel utilisation is where the HDI premium gets paid back.
Microvias at 75 µm.
Six layers deep,
every one of them holds.
Sequential lamination from 1+N+1 to 7+N+7. Drilling a small hole is not the hard part. Keeping a stacked via tower one solid copper column after thermal cycling is.
↓ Below is this board in section · six layers · 1.0 mm overall
75 µmStandard production microvia
3 / 3 milMinimum trace / space
30 layersMaximum layer count
Step 00 — What lands on the line
Four to thirty layers, and most of them thinner than you expect.
These are the shapes that actually come through: panel arrays, long strips with edge connectors, castellations, metal-core modules, rigid-flex tails. If your board looks like one of these, the stackup conversation is short.
Edge connector strip
Long, narrow, gold-finger edge. Registration across that length is the thing that decides yield, not the layer count.
Small-board strip
Six-up strips for pick-and-place. Small boards utilise a panel better, which is one of the few places HDI beats conventional on price.
Odd-form and castellation
Routed outlines, castellations, cut-outs. Worth telling us early — odd-form changes the routing and the fixture, not the stackup.
Multiple-up routing
Several designs on one panel. When two boards share a stackup, quoting them together is usually cheaper than quoting them apart.
Thin buildup stack
0.4–1.0 mm overall with 50–75 µm dielectric per layer. This is the shape most HDI projects actually arrive in.
Step 01 — Decide
Settle whether you need HDI before anything else.
Your BGA pitch decides it. At 0.8 mm and above, a conventional multilayer board is usually cheaper and faster. At 0.65 mm and below, microvias stop being an option and become the premise.
1.0 mmStandard through-hole vias are enoughNot HDI
0.8 mmThrough-hole or blind vias both routeType I (optional)
0.65 mmBlind or microvia — where HDI actually startsType I
0.5 mmMicrovia; fine-pitch escape starts to bindType I or II
0.4 mmStacked, copper-filled; via-in-pad requiredType II or III
0.3 mmAny-layer interconnect — the density ceilingType III / ELIC
Step 02 — The via
The hole is grown, not drilled.
A CO2 laser cannot cut through copper, so the copper window has to be opened first. A UV laser at 355 nm cuts both copper and dielectric and is what we use below 100 µm. Three steps after that are not optional: desmear, electroless copper seed, pattern plating to fill.
Then it gets planarised. Coplanarity is held inside 3 µm. Skip that and the next prepreg presses down over the via bump and seals air above it — a void you will never see.
Finished via ≈100 µm dia · 60–75 µm deep · top 75 µm tapering to ≈50 µm · aspect ratio < 1:1
Stacked microvias
Copper fill is not optional
Consecutive microvias line up into a tower. Without bottom-up copper fill there is nothing for the next layer to land on, so fill and planarisation are part of the structure rather than a finish. Highest density, and the step that most often decides the price.
No dimple > 5 µmCoplanarity 3 µm
Staggered microvias
Cheaper, and the right default
Each via offsets from the one below, so no copper fill is required. The cost is routing area, not reliability. On most boards this is what the stackup should use by default — reserve stacked vias for the areas where density genuinely binds.
No fill requiredUses more routing area
Step 03 — Stackup
Every additional buildup step costs two to three days.
1 step1+N+1 · 0.65 mm BGA · 4–30 layers8 days prototype
2 steps2+N+2 · 0.5 mm BGA · 6–30 layers10–11 days
3 steps3+N+3 · 0.4 mm BGA · 8–30 layers13–14 days
4 steps4+N+4 · any-layer · 10–30 layers16–17 days
5 steps5+N+5 · SiP / AI accelerator · 12–30 layers19–20 days
Step 03b — How the work is split
HDI goes to a line that runs HDI every day.
Core fabrication, buildup and through-hole drilling do not share a registration budget. That is the whole reason a board goes to one line rather than another, and it is what the numbers below are really about.
Registration, not machinery
Holding ±25 µm across a buildup layer is a discipline held on every panel. The laser is the same on both lines; the inspection frequency is not.
±25 µm HDI budget
Hybrid by default
Microvias in the buildup layers, mechanical through-holes for power and ground. Most HDI designs are hybrids, and that is the cost-effective way to build them.
Two via types, one board
Stackup engineering first
Via structure feasibility, aspect ratios and capture pad sizes are checked against your design before production. DFM comments come back with the quote, not with the first panel.
Before the panel is booked
Step 04 — Dielectric
The buildup dielectric sets the electrical behaviour and the service life.
FR-4 10802.8 mil cured · lead-free reflow compatibleDefault buildup layer
FR-4 21164.6 mil cured · lead-free reflow compatibleThicker dielectric
Megtron 6R-5775 · Df 0.004 at 10 GHzHigh speed, RF-adjacent
Isola 370HRTg 180 °CLead-free assembly reliability
Buildup dielectric runs 50–75 µm against 100–200 µm on a conventional board. At the same target impedance that means narrower traces, so the stackup model belongs in the quote request, not in the follow-up.
Send the Gerber. We will tell you whether HDI is the right call for this board, which step count you actually need, and which layer is the one that will hurt.
Engineering reply within 12 hours